Additional information
by Sanjay Churiwala (Editor)
Chapter 1: State of the Art Programmable Logic 1
Chapter 2: Vivado Design Tools 17Chapter 3: IP Flows 23Chapter 4: Gigabit Transceivers 35Chapter 5: Memory Controllers 49Chapter 6: Processor Options 65Chapter 7: Vivado IP Integrator 75Chapter 8: SysGen for DSP 85Chapter 9: Synthesis 97Chapter 10: C Based Design 111Chapter 11: Simulation 127Chapter 12: Clocking 141Chapter 13: Stacked Silicon Interconnect (SSI) 155Chapter 14: Timing Closure 167Chapter 15: Power Analysis and Optimization 179Chapter 16: System Monitor 191Chapter 17: Hardware Debug 205Chapter 18: Emulation Using FPGAs 221Chapter 19: Partial Reconfiguration & Hierarchical Design 239
Back Jacket
This book helps readers to implement their designs on Xilinx(R) FPGAs. The authors demonstrate how to get the greatest impact from using the Vivado(R) Design Suite, which delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. This book is a hands-on guide for both users who are new to FPGA designs, as well as those currently using the legacy Xilinx tool set (ISE) but are now moving to Vivado. Throughout the presentation, the authors focus on key concepts, major mechanisms for design entry, and methods to realize the most efficient implementation of the target design, with the least number of iterations.
Author Biography
Sanjay Churiwala is Senior Director of Engineering for Xilinx India Technology Services. He has extensive experience in the field of EDA and semiconductors R&D, as well as customer-interaction. He specializes in Clock Domain Crossings and Synchronization, STA, Power, Synthesis, Simulation, Rule based static checkers, Cell Characterization and Modeling.
