Additional information
by Saeideh Shirinzadeh (Author), Rolf Drechsler (Author)
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.
- Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;
- Describes automated compilation of programmable logic-in-memory computer architectures;
- Includes several effective optimization algorithm also applicable to classical logic synthesis;
- Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
Back Jacket
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.
- Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;
- Describes automated compilation of programmable logic-in-memory computer architectures;
- Includes several effective optimization algorithm also applicable to classical logic synthesis;
- Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
Author Biography
Saeideh Shirinzadeh received the B.Sc. (2010) and M.Sc. (2012) degrees in Electrical Engineering from University of Guilan, Iran. She is currently pursuing the Ph.D. degree at the group of computer architecture, University of Bremen, Germany. Her research interests include logic synthesis, in-memory computing, multi-objective optimization, and evolutionary computation.
Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from J.W. Goethe University Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and with the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he additionally became the Director of the Cyber-Physical Systems group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design. He is an IEEE Fellow.
